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| D16550 Configurable UART with FIFO ver 2.08 OVERVIEW The D16550 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit directions. D16550 performs serial-toparallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). D16550 includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16 x clock for driving the internal transmitter logic. Provisions are also included to use this 16 x clock to drive the receiver logic. The D16550 has complete MODEM control capability, and a processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link. The separate BAUD CLK line allow to set an exact transmission speed, while the UART All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl internal logic is clocked with the CPU frequency. Two DMA modes are supported: single transfer and multi-transfer. These modes allow UART to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers. The configuration capability allows user to enable or disable during Synthesis process the Modem Control Logic and FIFO's Control Logic, change the FIFO size. So in applications with area limitation and where the UART works only in 16450 mode, disabling Modem Control and FIFO's allow to save about 50% of logic resources. The D16550 has universal microcontroller interface, allows correct communication with D16550 no matter how D16550 clock is related to microcontroller clock. The core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices. Thanks to universal interface D16550 core implementation and verification are very simply, by eliminating a number of clock trees in complete system. Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. APPLICATIONS Serial Data communications applications Modem interface Technology Code independent HDL Source Full prioritized interrupt system controls Fully synthesizable static design with no internal tri-state buffers KEY FEATURES Software compatible with 16450 and 16550 UARTs Configuration capability Separate configurable BAUD clock line Two modes of operation: UART mode and FIFO mode Majority Voting Logic In the FIFO mode transmitter and receiver are each buffered with 16 byte FIFO to reduce the number of interrupts presented to the CPU Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data Independently controlled transmit, receive, line status, and data set interrupts False start bit detection 16 bit programmable baud generator MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD) Fully programmable characteristics: DESIGN FEATURES The functionality of the D16550 core was based on the Texas Instruments TL16C550A. The following characteristics differentiate the D16550 from Texas Instruments devices: The bi-directional data bus has been split into two separate buses: datai(7:0), datao(7:0) Signals rd2 and wr2, xin, and xout have been removed from interface Signal ADS and address latch have been removed The DLL, DLM and THR registers are reset to all zeros TEMT and THRE bits of Line Status Register, are reset during the second clock rising edge following a THR write RCLK clock is replaced by global clock CLK, internally divided by BAUD factor. Asynchronous microcontroller interface is replaced by equivalent Universal interface All latches implemented in original 16550 devices are replaced by equivalent flip-flop registers, with the same functionality serial-interface 5-, 6-, 7-, or 8-bit characters Even, odd, or no-parity bit generation and detection 1-, 11/2-, or 2-stop bit generation Baud generation Complete status reporting capabilities Line break generation and detection. Internal diagnostic capabilities: Loop-back controls for communications link fault isolation Break, parity, overrun, framing error simulation Two DMA Modes allows single and multitransfer http://www.DigitalCoreDesign.com http://www.dcd.pl All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance HDL Source to Netlist Single Design to Unlimited Designs CONFIGURATION The following parameters of the D16550 core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. * Baud generator * External RCLK source * External BAUDCLK source * Modem Control logic * SCR Register * FIFO Control logic enable disable enable disable enable disable enable disable enable disable enable disable Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation. Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. APPLICATION addr CPU ale addr latch addr(2:0) clk rst D16550 baudclk rclk so si rts dtr dsr dcd cts ri datao(7:0) datai(7:0) we rd cs int datai(7:0) datao(7:0) wr rd cs intr rxrdy txrdy out1 out2 EIA Drivers Single Design license for VHDL, Verilog source code called HDL Source Encrypted, or plain text EDIF called Netlist baudclken rclken One Year license for Encrypted Netlist only Typical D16550 and processor connection is shown in figure above. Unlimited Designs license for HDL Source Netlist Upgrade from http://www.DigitalCoreDesign.com http://www.dcd.pl All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. SYMBOL rst clk rclk baudclk datai(7:0) address(2:0) wr rd cs si cts dsr dcd ri baudclken rclken baudout intr datao(7:0) ddis txrdy rxrdy so rts dtr out1 out2 BLOCK DIAGRAM Data Bus Buffer - The data Bus Buffer accepts inputs from the system bus and generates control signals for the other D16550 functional blocks. Address bus ADDR(2:0) selects one of the register to be read from/written into. Both RD and WE signals are active low, and are qualified by CS; RD and WE are ignored unless the D16550 has been selected by holding CS low. D16550 addr(2:0) datai(7:0) datao(7:0) rd wr cs ddis txrdy rxrdy Data Bus Buffer Receiver Control & Shift Register rclk rclken si PINS DESCRIPTION PIN rst clk datai[7:0] addr[2:0] cs wr rd rclk baudclk si cts dsr dcd ri baudclken rclken baudout datao[7:0] so ddis txrdy rxrdy rts dtr out1 out2 intr RCVR Buffer & RCVR FIFO TYPE input input input input input input input input input input input input input input input input output output output output output output output output output output output DESCRIPTION Global reset Global clock Parallel data input Address bus Chip select input Write input Read input Receiver clock Baud generator clock Serial data input Clear to send input Data set ready input Data carrier detect input Ring indicator input Baud generator clock enable Receiver clock enable Baud generator output Parallel data output Serial data output Driver disable output Transmitter ready output Receiver ready output Request to send output Data terminal ready output Output 1 Output 2 Interrupt request output rts cts dtr dsr dcd ri out1 out2 Modem control logic Transmitter Control & Shift Register so baudclk baudclken baudout clk rst THR Buffer & THR FIFO Baud Generator Interrupt Controller intr Baud Generator - The D16550 contains a programmable 16 bit baud generator that divides clock input by a divisor in the range between 1 and (216-1). The output frequency of the baud generator is 16x the baud rate. The formula for the divisor is: divisor = frequency baudrate * 16 Note: When enabled RCLK and BAUDCLK pins frequency should be at least two times lower than CLK, 2*fRCLK< fCLK All trademarks mentioned in this document are trademarks of their respective owners. Two 8-bit registers, called divisor latches DLL and DLM, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the D16550 in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded on the CLK rising edge following the write to http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. DLL or DLM to prevent long counts on initial load. Modem Control Logic controls the interface with the MODEM or data set (or a peripheral device emulating a MODEM). Interrupt Controller - D16550 consists fully prioritized interrupt system controller. It controls interrupt requests to the CPU and interrupt priority. Interrupt controller contains Interrupt Enable (IER) and Interrupt Identification (IIR) registers. Receiver Control - Receiving starts when the falling edge on Serial Input (SI) during IDLE State is detected. After starting the SI input is sampled every 16 internal baud cycles as it is shown in figure below. When the logic 1 state is detected during START bit it means that the False Start bit was detected and receiver back to the IDLE state. Receiver FIFO - The Rx FIFO is 16 levels deep, it receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error flag. Transmitter Control module controls transmission of written to THR (Transmitter Holding register) character via serial output SO. The new transmission starts on the next overflow signal of internal baud generator, after writing to THR register or Transmitter FIFO. Transmission control contains THR register and transmitter shift register. Transmitter FIFO - the Tx portion of the UART transmits data through SO as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt. PERFORMANCE The following table gives a survey about the Core area and performance in the ALTERA(R) devices after Place & Route: Speed grade CYCLONE -6 CYCLONE 2 -6 STRATIX -5 STRATIX 2 -3 STRATIXGX -5 MERCURY -5 EXCALIBUR -1 APEX II -7 APEX20KC -7 APEX20KE -1 APEX20K -1V ACEX1K -1 FLEX10KE -1 Device 1 Logic Cells 452 4611 4521 3881 4521 5131 4791 4801 4791 4791 4791 5001 5001 1 Fmax 153 MHz 165 MHz 189 MHz 241 MHz 184 MHz 134 MHz 131 MHz 157 MHz 141 MHz 123 MHz 94 MHz 104 MHz 102 MHz - FIFOs implemented in EAB's - 304 Bits Core performance in ALTERA(R) devices All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. D16X50 UARTS FAMILY OVERVIEW The family of DCD D16X50 UART IP Cores combine a high-performance, low cost, and small compact size, offering the best price/performance ratio in the IP Market. The DCD's Cores are dedicated for use in cost-sensitive consumer products, computer peripherals, office automation, automotive control systems, security and telecommunication applications. The D16X50 IP Cores are written in pure VHDL/VERILOG HDL languages which make them technologically independent. All of the D16X50 IP Cores can be fully customized according to customer needs. Prioritized interrupt system Internal diagnostic capabilities D16450 D16550 D16750 D16552 D16752 D16754 1 1 1 2 2 4 - 2* 16 2* 64 4* 16 4* 64 8* 64 - - -* -* -* -* -* IRDA Port Design *-Optional D16X50 family of Configurable UARTs with FIFO IP Cores All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. 1284 Parallel Port -* -* -* -* -* FIFO Size (Bytes) Break generation and detection Complete status reporting False START Bit detection MODEM Control Separate BAUD Clock line UARTS number RTS/CTS Flow Control Majority voting logic Software Flow Control FIFO Mode of operation UART Mode CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND nfo@dcd.pl e-mail: iinfo@dcd.pl tel. fax : +48 32 282 82 66 : +48 32 282 74 37 Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. |
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